The IEEE1588 protocol was initially used for the description of the accurate time synchronization protocol in network measurement and control system and has been widely applied in the Ethernet field with the development of Ethernet technology.
In prior technology, it is possible to accurately process IEEE1588 protocol in 100 Gbit/s Ethernet. The method includes adding the timestamp of the time into downstream Ethernet frame, or marking the received timestamp of the frame in response to receiving the upstream Ethernet frame receives, under the control of relevant controlling signals of the IEEE1588 protocol when the Ethernet frame is being transmitted through PHY layer (Physical Layer).
Based on the description of IEEE1588 protocol, the closer to PHY layer the position where the timestamp is added to or obtained from the data frame, the more accurate the position is. Because a farther location may cause jitters due to frequency difference or FIFO on data path and the closer location may more accurately show the actual time when the frame is received and transmitted.
FIG. 1 shows a connection of MAC and PCS (Physical coding sublayer) in 10 Gbit/s Ethernet of prior technology. In the downstream direction, MAC (Media Access Control) sublayer 2 transmits the data to PCS 1 where the data is coded and then transmitted to 64/16 transformer 3; in the downstream direction, PCS 1 comprises at least an asynchronous FIFO 12 and a PCS transmitting module (PCS TX) 14 which at least comprises a 64/66B encoding module and a scrambling module. In the upstream direction, 16/64 transformer 4 transmits the data to PCS 1 where the data is decoded and then transmitted to MAC sublayer 2; in the upstream direction, PCS 1 at least comprises an asynchronous FIFO 16 and a PCS receiving module (PCS RX) 18 which at least comprises a 64/66B decoding module and a descrambling module. It is obvious that the Ethernet has evolved to 10 Gbit/s and includes a range of features not in the 100 Mbit/s Ethernet: for example, 10 Gbit/s Ethernet MAC sublayer provides dynamic frame clearance adjustment. It also supports asynchronous FIFO for removing frequency differences between the MAC sublayer and the 10 Gbit/s Ethernet PCS, and the PCS (generally 10 GBASE-R PCS) clock has nicks (e.g. 1 invalid clock cycle every 33 clock cycles). Besides, difference in 10 Gbit/s and 100 Mbit/s Ethernet can also be found in other disclosed documents. The inventor has also realized that the prior technology cannot accurately manage (adding or obtaining) timestamp in 10 Gbit/s Ethernet.